mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 102

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 63:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Command
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
WRITE-to-READ
Notes:
WL - t DQSS
WL ± t DQSS
WL + t DQSS
NOP
T1
1.
2. Subsequent rising DQS signals must align to the clock within
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet
t
between module ranks.
t
greater.
WTR is required for any READ following a WRITE to the same device, but it is not required
WTR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T2
DI
b
DI
b
T2n
2
NOP
T3
2
2
T3n
NOP
T4
102
t WTR 1
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WTR is either 2 or
Bank a,
READ
Col n
T6
1Gb: x4, x8, x16 DDR2 SDRAM
CL = 3
CL = 3
CL = 3
T7
NOP
Transitioning Data
t
DQSS.
©2003 Micron Technology, Inc. All rights reserved.
t
WTR/
T8
NOP
t
CK, whichever is
Operations
T9
NOP
Don’t Care
DI
DI
DI
T9n