mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 79

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Power-Down Mode
CAS Latency (CL)
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Active power-down (PD) mode is defined by bit M12, as shown in Figure 38 on page 77.
PD mode allows the user to determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in Table 11 on page 27.
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 38 on page 77. CL is
the delay, in clock cycles, between the registration of a READ command and the avail-
ability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may
result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This
feature allows the READ command to be issued prior to
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
further detail in “Posted CAS Additive Latency (AL)” on page 83.
Examples of CL = 3 and CL = 4 are shown in Figure 39 on page 80; both assume AL = 0. If
a READ command is registered at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n + m (this assumes AL = 0).
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
79
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
t
RCD (MIN) by delaying the
DD
3P normal and I
©2003 Micron Technology, Inc. All rights reserved.
Operations
DD
3P low-