mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 97

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 58:
WRITE
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
LDQS, LDQS#/UDQ, UDQS# 3
All DQs collectively 4
DQ (first data valid)
DQ (last data valid)
Data Output Timing –
DQS, DQS# or
Notes:
Note:
CK#
CK
1. READ command with CL = 3, AL = 0 issued at T0.
2.
3. DQ transitioning after DQS transitions define
4. All DQ must transition by
5.
6.
7.
8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, but
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL
minus one clock cycle (WL = RL - 1CK) (see "READ" on page 71). The starting column
and bank addresses are provided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto precharge is enabled, the row being
accessed is precharged at the completion of the burst.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(
Figure 59 on page 99 shows the nominal case and the extremes of
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
T0 1
t
t
DQSS [MIN] and
DQSS.
For the WRITE commands used in the following illustrations, auto precharge is dis-
abled.
t
skew.
t
t
t
to when the device begins to drive or no longer drives, respectively.
DQSCK is the DQS output window relative to CK and is the long-term component of DQS
AC is the DQ output window relative to CK and is the “long term” component of DQ skew.
LZ (MIN) and
HZ (MAX) and
t
DQSS is specified with a relatively wide range (25 percent of one clock cycle).
T1
t
AC and
t LZ (MIN)
t
AC (MIN) are the first valid signal transitions.
t
AC (MAX) are the latest valid signal transitions.
t
DQSS [MAX]) might not be intuitive, they have also been included.
t
DQSCK
T2
t
DQSQ after DQS transitions, regardless of
t RPRE
97
t LZ (MIN)
t DQSCK 2 (MIN) t DQSCK 2 (MAX)
T3
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3n
T3n
t AC 5 (MIN)
T3n
T3n
t
DQSQ window.
T4
T4
1Gb: x4, x8, x16 DDR2 SDRAM
T4
T4
T4n
T4n
T4n
t AC 5 (MAX)
T4n
T5
T5
T5
©2003 Micron Technology, Inc. All rights reserved.
T5
T5n
t
DQSS for BL = 4. Upon
T5n
t
T5n
AC.
T5n
T6
T6
T6
Operations
t HZ (MAX)
T6
T6n
t
T6n
t RPST
DQSS.
T6n
t HZ (MAX)
T6n
T7