mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 14

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 3:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1Gb_DDR2_x4x8x16_D2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
G8, G2, H7,
H3, H1, H9,
A1, E1, M9,
C2, D7, D3,
D1, D9, B1,
F1, F9, C8,
Number
x16 Ball
K7, L7,
B7, A8
F3, B3
F7, E8
R1, J9
K9
K3
B9
–
–
–
–
FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued)
A1, E9, L1, H9
x4, x8 Ball
D3, D1, D9,
C8, C2, D7,
C8, C2, D7,
Number
F7, G7,
B7, A8
B3, A2
B1, B9
D3
B3
F9
F3
–
–
–
UDQS, UDQS#
RDQS, RDQS# Output Redundant data strobe: For 128 Meg x 8 only. RDQS is
DQ12–DQ14,
LDQS, LDQS#
RAS#, CAS#,
DQ9–DQ11,
LDM, UDM
DQS, DQS#
DQ0–DQ2,
DQ3–DQ5,
DQ6–DQ8,
DQ0–DQ2,
DQ3–DQ5,
DQ0–DQ2,
DQ6–DQ7
Symbol
DQ15
ODT
WE#
DQ3
V
DM
DD
Supply Power supply: 1.8V ±0.1V.
Input
Input
Input
Type
I/O
I/O
I/O
I/O
I/O
I/O
Description
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM balls are input-only, the DM loading is
designed to match that of DQ and DQS balls. LDM is DM for
lower byte DQ0–DQ7 and UDM is DM for upper byte
DQ8–DQ15.
On-die termination: ODT (registered HIGH) enables
termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each of the following balls:
DQ0–DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for
the x16; DQ0–DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the
x8; DQ0–DQ3, DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
Data input/output: Bidirectional data bus for 64 Meg x 16.
Data input/output: Bidirectional data bus for 128 Meg x 8.
Data input/output: Bidirectional data bus for 256 Meg x 4.
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center-aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data strobe for lower byte: Output with read data, input
with write data for source synchronous operation. Edge-aligned
with read data, center-aligned with write data. LDQS# is only
used when differential data strobe mode is enabled via the
LOAD MODE command.
Data strobe for upper byte: Output with read data, input
with write data for source synchronous operation. Edge-aligned
with read data, center-aligned with write data. UDQS# is only
used when differential data strobe mode is enabled via the
LOAD MODE command.
enabled/disabled via the LOAD MODE command to the
extended mode register (EMR). When RDQS is enabled, RDQS is
output with read data only and is ignored during write data.
When RDQS is disabled, ball B3 becomes data mask (see DM
ball). RDQS# is only used when RDQS is enabled and differential
data strobe mode is enabled.
14
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Ball Assignments and Descriptions
1Gb: x4, x8, x16 DDR2 SDRAM
©2004 Micron Technology, Inc. All rights reserved.