mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 68

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
10. A WRITE command may be applied after the completion of the READ burst.
5. The following states must not be interrupted by any executable command (DESELECT or
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
NOP commands must be applied on each positive clock edge during these states):
Refresh:
Accessing mode
register:
Precharge all:
precharge enabled and READs or WRITEs with auto precharge disabled.
valid state for precharging.
Starts with registration of a REFRESH command and ends when
met. After
state.
Starts with registration of the LOAD MODE command and ends when
t
the all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends
when
MRD has been met. After
t
RP is met. After
68
t
RFC is met, the DDR2 SDRAM will be in the all banks idle
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, all banks will be in the idle state.
t
MRD is met, the DDR2 SDRAM will be in
1Gb: x4, x8, x16 DDR2 SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Commands
t
RFC is