HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 71

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
8
8.1
Table 6: Activation/deactivation layer 1 for finite state matrix for NT
/
|
Note 1: Timer 1 (T1) is not implemented in the HFC-SP and must be implemented in software.
Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125µs). This implies
Note 3: After reset the state machine is fixed to G0.
:Q^eQbi " !
Event
State machine release
(Note 3)
Activate request
Deactivate request
Expiry T2
(Note 2)
Receiving INFO 0
Receiving INFO 1
Receiving INFO 3
*
Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This
prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data.
hint!
State matrices for NT and TE
S/T interface activation/deactivation layer 1 for finite state matrix for NT
No state change
Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons
Impossible by the definition of the physical layer service
that a TE has to recognize INFO 0 and to react on it within this time.
State number
State name
INFO
sent
(Note 1)
INFO 0
Reset
G0
G2
G2
]
]
]
]
]
Deactive
(Note 1)
(Note 1)
INFO 0
G1
G2
G2
]
]
|
|
/
Start timer T2
activation
Pending
(Note 1)
INFO 2
G2
G4
G3
]
]
]
|
|
Start timer T2
INFO 4
Active
G3
G4
]
G2
]
|
|
/
deactivation
Pending
(Note 1)
INFO 0
G4
G2
G1
G1
]
]
|
|
Cologne
Chip
'! _V (#