HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 61

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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6.3
Figure 7: GCI/IOM2 bus clock and data alignment
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SYMBOL
t
t
t
t
t
t
t
t
SRD
SRDH
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
SRWRA
*)
**)
Double clock mode with 24.576MHz
OSC_IN should be symmetrical so t
GCI/IOM2 bus clock and data alignment for Mitel ST
Data Out Stable after OSC_IN
Data Out Stable Hold Time after OSC_IN
Data In Setup Time to OSC_IN
Data In Hold Time after OSC_IN
Delay Time OSC_IN
Delay Time OSC_IN
Data Hold Time after /SRWR
Address Hold Time after /SRWR
CHARACTERISTICS
Ç
Ç
to /SRWR Low
to /SRWR High
LOW
Ç
Ç
= t
Ç
HIGH
Ç
TM
bus
t
MIN.
CLK
10ns
20ns
5ns
0ns
5ns
5ns
1ns
/ 3
Cologne
Chip
MAX.
30ns
15ns
15ns
–
–
–
–
–
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