HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 52

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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Name
CTMT
CHIP_ID
B_MODE
Addr.
19h
16h
13h
Bits
4..2
3..0
7..4
1..0
0
1
5
6
7
2
3
4
5
6
7
r/w Function
w
w
w
w
w
w
w
w
w
w
w
w
w
r
r
HDLC/transparent mode for B1-channel
'0' HDLC mode (reset default)
'1' transparent mode
HDLC/transparent mode for B2-channel
'0' HDLC mode (reset default)
'1' transparent mode
select timer and watchdog (bit 4 = MSB)
'000'
'001'
'010'
'011'
'100'
'101'
'110'
'111'
timer/watchdog reset mode
'0' reset timer/WD by CTMT bit 7 (reset default)
'1' automatically reset timer/WD at each access to HFC-SP
ignored
reset timer/WD
'1' reset timer/WD
This bit is automatically cleared.
IRQ assigned by the PnP BIOS
Bits [2:0] of the CIRM register must be set to the value
corresponding to the hardware connected IRQ lines.
These bits are only valid in ISA Plug and Play mode.
Chip identification
1001b
unused
in 64 kbit/s mode: bit is ignored
in 56 kbit/s mode: value of the LSB in 7-bit mode
unused
56 kbit/s mode selection bit for B1-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
56 kbit/s mode selection bit for B2-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
'0' Data not inverted for B1-channel (reset default)
'1' Data inverted for B1-channel
'0' Data not inverted for B2-channel (reset default)
'1' Data inverted for B2-channel
timer
3.125ms
6.25ms
12.5ms
25ms
50ms
400ms
800ms
off
HFC-SP
watchdog
off
6.25ms
12.5ms
25ms
50ms
100ms
800ms
1600ms
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Cologne
Chip