HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 31

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.6.3 Registers of the GCI/IOM2 bus section
GCI/IOM2 bus timeslot selection registers
GCI/IOM2 bus timeslot selection registers
GCI/IOM2 bus data registers
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CIP / I/O-address
00000010
00000011
00001010
00001011
CIP / I/O-address
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
CIP / I/O-address
00101000
00101001
00101010
00101011
*)
**)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the
S/T controller and need not be accessed by the user.
These registers can also be accessed by DMA
02h
03h
0Ah
0Bh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
Name
Name
AUX1_SSL
AUX2_SSL
Name
B1_D
B2_D
AUX1_D
AUX2_D
C/I
TRxR
MON1_D
MON2_D
B1_SSL
B2_SSL
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
*)
*)
**)
**)
r/w
r/w
r
r/w
r/w
r/w
w
w
w
w
w
w
w
w
r/w
r/w
r/w
r/w
r/w
Function
C/I command/indication register
Monitor Tx ready handshake
first monitor byte
second monitor byte
Function
B1-channel transmit slot (0..31)
B2-channel transmit slot (0..31)
AUX1-channel transmit slot (0..31)
AUX2-channel transmit slot (0..31)
AUX1-channel receive slot (0..31)
AUX2-channel receive slot (0..31)
Function
GCI/IOM2 bus B1-channel data register
GCI/IOM2 bus B2-channel data register
AUX1-channel data register
AUX2-channel data register
B1-channel receive slot (0..31)
B2-channel receive slot (0..31)
Cologne
Chip
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