HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 35

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.9.1 FIFO channel operation
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel)
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FIFO change, FIFO reset and F1/F2 incrementation
Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY
period of the HFC-SP. This means an access to FIFO control registers is NOT allowed until BUSY
status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs).
Status, interrupt and control registers can be read and written at any time.
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The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs.
If 8k RAM mode is selected counter state 1A00h of the Z-counters follows counter state 1FFFh in
the B-channel FIFOs.
The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs.
The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs.
The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
important!
important!
Cologne
Chip
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