HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 19

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.2.2 ISA Plug and Play control registers
3.2.2.1 Card level control regsisters
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control register
Plug and Play
address
00h
01h
02h
03h
*)
This is an extension to the Plug and Play Specification
Write
Read
w
w
w
r
Accessable in state
Isolation state,
Isolation state,
Isolation state
Config state
Isolation state
Config state
Config state
Sleep state,
Sleep state,
*)
Set read data port address register. Bits[7:0]
become bits[9:2] of the port's I/O address. Bits[11:10]
are hardwired to 00b and bits[1:0] are hardwired to
11b.
Serial isolation register. Used to read the serial
identifier during the card isolation process.
Configuration
reserved and must be zero. The defined bits are:
0
1
2
All bits are automatically cleared by the hardware.
Wake command register. Writing a CSN to this
register has the following effects:
-
-
Any write to a card's wake command register with a
match on its CSN causes the pointer to the serial
identifier / resource data to be reset to the first byte of
the serial identifier.
Reset Bit. When set to one, resets all of the
card's configuration registers to their default
state. The CSN is not affected.
Return to wait for key state. When set to one,
all cards return to wait for key state.
Their CSNs and configuration registers are not
affected. This command is issued after all cards
have been configured and activated.
Reset CSN to zero. When set to one, all cards
reset their CSN to zero.
If the value written is 00h, all cards in the sleep
state with a CSN=00h go to the isolation state.
Any card in configure state (CSN not 00h) goes
to the sleep state.
If the value written is not 00h, any card in the
sleep state with a matching CSN goes to
configure state. Any card in the isolation state
goes to sleep state.
control
Description
register.
Bits[7:3]
Cologne
Chip
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