HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 4

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.9
3.10
3.11
3.12
3.13
4
4.1
4.2
4.3
4.4
4.5
5
6
6.1
6.2
6.3
6.4
6.5
6.6
7
7.1
7.2
7.3
7.4
8
8.1
8.2
9
9.1
9.2
10
10.1
10.2
11
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3.9.1
3.9.2
6.4.1
6.4.2
3.9.1.1
3.9.1.2
3.9.1.3
3.9.1.4
3.9.1.5
3.9.1.6
Register bit description.................................................................................................................... 43
Electrical characteristics ................................................................................................................. 56
Timing characteristics ..................................................................................................................... 59
S/T interface circuitry...................................................................................................................... 66
State matrices for NT and TE ......................................................................................................... 71
Binary organisation of the frames .................................................................................................. 73
Clock synchronisation...................................................................................................................... 75
HFC-SP package dimensions .......................................................................................................... 77
FIFOs ............................................................................................................................................. 34
Register bit description of the FIFO select register ....................................................................... 43
Register bit description of S/T section .......................................................................................... 43
Register bit description of GCI/IOM2 bus section ........................................................................ 47
Register bit description of CONNECT register............................................................................. 50
Register bit description of interrupt, status and control registers.................................................. 51
ISA-PC bus or processor access .................................................................................................... 59
SRAM access................................................................................................................................. 60
GCI/IOM2 bus clock and data alignment for Mitel ST
GCI/IOM2 timing .......................................................................................................................... 62
EEPROM access ............................................................................................................................ 64
Access to an external device.......................................................................................................... 65
External receiver circuitry ............................................................................................................. 66
External transmitter circuitry......................................................................................................... 67
Oscillator circuitry ......................................................................................................................... 70
EEPROM circuitry......................................................................................................................... 70
S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 71
Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 72
S/T frame structure ........................................................................................................................ 73
GCI frame structure ....................................................................................................................... 74
External SRAM ......................................................................................................................... 40
Connecting an external device to the HFC-SP .......................................................................... 41
Power down considerations....................................................................................................... 41
Configuring test loops ............................................................................................................... 42
Clock synchronisation in NT-mode........................................................................................... 75
Clock synchronisation in TE-mode ........................................................................................... 76
FIFO channel operation......................................................................................................... 35
Transparent mode of HFC-SP ............................................................................................... 39
Master mode.......................................................................................................................... 62
Slave mode ............................................................................................................................ 63
Send channels (B1, B2 and D transmit)............................................................................ 36
Automatically D-channel frame repetition ....................................................................... 36
FIFO full condition in send channels................................................................................ 36
Receive Channels (B1, B2 and D receive) ....................................................................... 37
FIFO full condition in receive channels ........................................................................... 38
FIFO reset ......................................................................................................................... 39
TM
bus....................................................... 61
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Cologne
Chip