HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 41

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.11
It is possible to connect an external device parallel to the SRAM to the HFC-SP.
Figure 5: Connecting an external device to the HFC-SP
The external device is accessed when bit 6 in the CIP is set. Then bit[5:0] are the address select lines for
the external device.
3.12
For very low power consumption the oscillator of the HFC-SP can be stopped. Furthermore the external
SRAM is disabled (/SR_CS=1). To avoid current generated by floating inputs the data bus of the SRAM
and all other inputs must be put to GND or VDD. So it is useful to connect the SRAM data bus to a
resistor array of about 1M . If the HFC-SP is operated in processor mode the unused interrupt lines (and
watchdog lines) should not be left open. They should be connected to VDD or GND over a resistor to
reduce current.
If the oscillator is stopped and the awake option is disabled the supply current is reduced to less than
1mA.
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Connecting an external device to the HFC-SP
Power down considerations
Cologne
Chip
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