HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 62

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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6.4
Timing diagram 3: GCI/IOM2 timing
6.4.1 Master mode
To configure the HFC-SP as GCI/IOM2 bus master bit 0 of the MST_MODE register must be set. In this
case C4IO and F0IO are outputs.
&" _V (#
SYMBOL
t
t
t
t
t
C4P
C4H
C4L
C2P
C2H
*)
GCI/IOM2 timing
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set
F0IO is also awaited one C4IO clock cycle earlier.
Clock C4IO period (4.096 MHz)
Clock C4IO High Width
Clock C4IO Low Width
Clock C2O Period
Clock C2O High Width
CHARACTERISTICS
180 ns
78 ns
78 ns
360 ns
180 ns
MIN.
*)
*)
*)
244.14 ns
488.28 ns
244.14 ns
122 ns
122 ns
TYP.
*)
*)
*)
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Cologne
Chip
166 ns
308 ns
166 ns
616 ns
308 ns
MAX.
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*)