HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 25

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.4.1 DMA access in processor mode
In processor mode a simple DMA access to the auxiliary channels of the GCI/IOM2 interface is possible.
This is useful for tone synthetisation or for voice recording. DMAREQ is asserted every 125µs.
DMAREQ is reset when /DMAAK is active.
Table 3: DMA access in processor mode
*)
:Q^eQbi " !
1-pulse latches I/O address.
Mode
2,3,4
*
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the read/write
enables is inverted. This means a read command on the controller databus writes the AUX-
Channel register and a write command reads the register. The address on the address bus (SA0-
SA7) is ignored.
*
If DMA is not used /DMAAK0 and /DMAAK1 must be connected to VDD.
2
2
3
3
4
4
note
important!
/DMAAK0
1
0
1
0
1
0
1
/DMAAK1
1
1
0
1
0
1
0
/CS
X
X
X
X
X
X
X
ALE /IOR
0
0
X
1
1
0
0
*)
*)
/DS
X
X
X
0
0
0
0
/IOW
R/W
X
1
1
1
1
1
1
Function
no DMA
DMA write AUX1
DMA write AUX2
DMA write AUX1
DMA write AUX2
DMA write AUX1
DMA write AUX2
Cologne
Chip
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