HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 37

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31
frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-SP to manage more
frames even if the frames are very small.
The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the
B-channels.
3.9.1.4 Receive Channels (B1, B2 and D receive)
The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is
converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus
interface.
The HFC-SP checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not
generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is
converted by the HFC-SP into plain data. After the ending flag of a frame the HFC-SP checks the HDLC
CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named
STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the
end of the frame.
Figure 4: FIFO Data Organisation
The ending flag of a HDLC-frame can also be the starting flag of the next frame.
After a frame is received completely F1 is incremented by the HFC-SP automatically and the next frame
can be received.
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Cologne
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