HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 28

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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3.6
In ISA-PC mode, ISA Plug and Play mode and PCMCIA mode all registers are selected by writing the
register address into the Control Internal Pointer (CIP) register. This is done by writing the HFC-SP on
the higher I/O address (SA0 = 1).
All consecutive read or write data accesses (SA0 = 0) are done with the selected register until the CIP
register is changed.
In processor mode all registers can be directly accessed. The registers are selected by SA0 - SA7.
3.6.1 FIFO control registers
The FIFO control registers are used to select and control the FIFOs of the HFC-SP. In processor mode
the value is the address which directly selects the corresponding register.
The FIFO register selection is independent of the B- or D-channel FIFO number.
The FIFO is selected by the FIFO select register.
3.6.1.1 FIFO select register
3.6.1.2 FIFO registers
"( _V (#
CIP / I/O-address
00010000
CIP / I/O-address
100000xx
100001xx
100010xx
100011xx
101010xx
101011xx
101100xx
101101xx
101110xx
101111xx
*)
Internal HFC-SP register description
only in HDLC mode; In transparent mode (see also: 3.9.2) the frame counters F1 and F2 must
not be incremented.
10h
80h
84h
88h
8Ch
A8h
ACh
B0h
B4h
B8h
BCh
Name
FIF_SEL
Name
FIF_Z1L
FIF_Z1H
FIF_Z2L
FIF_INC_F1
FIF_F1
FIF_F2
FIF_INC_F2
FIF_DRD
FIF_Z2H
FIF_DWR
*)
*)
r/w
r/w
r
r
r
r
r
r
w
r
r
w
r
Function
FIFO selection
Function
FIFO input counter (Z1) low byte
FIFO input counter (Z1) high byte
FIFO output counter (Z2) low byte
FIFO output counter (Z2) high byte
read this register to increment frame counter F1
data write into FIFO and increment Z1
FIFO input HDLC frame counter (F1)
FIFO output HDLC frame counter (F2)
read this register to increment frame counter F2
data read out of FIFO and increment Z2
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Cologne
Chip