HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 33

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.7
The HFC-SP includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer
counter is incremented every 125µs. It can be reset by bit 7 of of the CTMT register. Furthermore the
timer is reset at every HFC-SP access when bit 5 of the CTMT register is set. Seven different timer
values can be selected.
3.8
(only available in processor mode)
The watchdog outputs of the HFC-SP are activated if the timer interrupt bit is active (not reset by reading
INT_S1) and the timer elapses a second time.
The reset of the timer counter itself and the watchdog value can be programmed in the CTMT register. In
automatic reset mode the watchdog/timer is reset by every access to the HFC-SP.
:Q^eQbi " !
Timer
Watchdog
Cologne
Chip
## _V (#