HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 65

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
6.6
Timing diagram 5: Access to an external device
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SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
EXT
LOW
HIGH
SRA
SRAH
SRD
SRDH
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
SRWRA
**)
**)
*)
**)
Access to an external device
Double clock mode with 24.576MHz
Clock should be symmetrical so t
Clock Cycle Time
Access to External Device Cycle Time
Clock Low Level Width
Clock High Level Width
Address Stable after Clock
Address Stable Hold Time after Clock
Data Out Stable after Clock
Data Out Stable Hold Time after Clock
Data In Setup Time to Clock
Data In Hold Time after Clock
Delay Time Clock
Delay Time Clock
Data Hold Time after /SRWR
Address Hold Time after /SRWR
CHARACTERISTICS
Ç
Ç
to /SRWR Low
to /SRWR High
LOW
Ç
Ç
= t
Ç
HIGH
Ç
Ç
Ç
4 x t
t
t
t
1/ f
MIN.
CLK
CLK
CLK
10ns
20ns
2ns
1ns
5ns
0ns
5ns
5ns
1ns
CLK
/ 3
/ 3
/ 3
CLK
Cologne
Chip
MAX.
15ns
30ns
15ns
15ns
–
–
–
–
–
–
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