HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 30

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

863 C@
3.6.2 Registers of the S/T section
# _V (#
CIP / I/O-address
00110000
00110001
00110010
00110011
00110100
00110111
00111100
00111101
00111110
00111111
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or
GCI/IOM2 bus controller and need not be accessed by the user. To read/write data the FIFO
registers should be used.
30h
31h
32h
33h
34h
37h
3Ch
3Dh
3Eh
3Fh
Name
STATES
SCTRL
SCTRL_E
SCTRL_R
SQ_REC
SQ_SEND
B1_REC
B1_SEND
B2_REC
B2_SEND
D_REC
D_SEND
E_REC
CLKDEL
*)
*)
*)
*)
*)
*)
*)
r/w
r
w
r
w
r
w
r
r/w
w
w
w
r
w
w
Function
State of the TE/NT state machine
S/T control register
S/T control register (extended)
receive enable for B-channels
receive register for S/Q bits
send register for S/Q bits
setup of the delay time between receive and
send direction (TE)
receive data sample time (NT)
B1-channel receive register
B1-channel transmit register
B2-channel receive register
B2-channel transmit register
D-channel receive register
D-channel transmit register
E-channel receive register
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Cologne
Chip