HFC-SP Cologne Chip AG, HFC-SP Datasheet - Page 63

• Manufacturer Part Number: HFC-SP
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

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All specifications are for 2.048 Mb/s Streams and f
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6.4.2 Slave mode
To configure the HFC-SP as GCI/IOM2 bus slave bit 0 of the MST_MODE register must be cleared
(reset default). In this case C4IO and F0IO are inputs.
All specifications are for 2.048 Mb/s Streams and f
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SYMBOL
t
t
t
t
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
C2L
F0iW
SToD
F0iCYCLE
C4P
C4H
C4L
C2P
C2H
C2L
F0iS
F0iH
F0iW
STiS
STiH
If the S/T interface is synchronized from C4IO (NT mode) the frequency must be stable to
Time depends on accuracy of OSC_IN frequency. Because of clock adjustment in the 31st time
slot these are the worst case timings when C4IO is adjusted.
Clock C2O Low Width
F0IO Width
STIO1/2 Delay fom C4IO
F0IO Cycle Time
Clock C4IO period (4.096 MHz)
Clock C4IO High Width
Clock C4IO Low Width
Clock C2O Period
Clock C2O High Width
Clock C2O Low Width
F0IO Setup Time to C4IO
F0IO Hold Time after C4IO
F0IO Width
STIO2 Setup Time
STIO2 Hold Time
CHARACTERISTICS
CHARACTERISTICS
Short F0IO
Long F0IO
1 half clock adjust
2 half clocks adjust
Level 1 Output
CLK
CLK
= 12.288 Mhz.
= 12.288 Mhz.
124.955 us 125.000 us 125.045 us
124.910 us 125.000 us 125.090 us
180 ns
230 ns
460 ns
MIN.
MIN.
20 ns
20 ns
25 ns
25 ns
20 ns
20 ns
40 ns
20 ns
20 ns
244.14 ns
488.28 ns
244.14 ns
244 ns
488 ns
TYP.
TYP.
10 ns
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Cologne
Chip
260 ns
MAX.
308 ns
520 ns
MAX.
25 ns
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10
-4
.