SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 856
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 856 of 1109
- Download datasheet (17Mb)
42.3
42.3.1
42.3.2
42.3.3
42.4
42.4.1
856
Product Dependencies
Functional Description
AT91SAM9263
I/O Lines
Power Management
Interrupt
Host Controller Interface
Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
Warning: A pull-down must be connected to DP on the board. Otherwise the USB host will per-
manently detect a device connection on this port.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceiv-
ers are controlled by the USB host controller.
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a
correct accuracy of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller
(PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the
UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller
(AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the USB Host Controller.
The Host Controller is the target for all communications on this channel. The operational regis-
ters contain control, status and list pointer registers. They are mapped in the memory mapped
area. Within the operational register set there is a pointer to a location in the processor address
space named the Host Controller Communication Area (HCCA). The HCCA is the second com-
munication channel. The host controller is the master for all communication on this channel. The
HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to
the done queue and status information associated with start-of-frame processing.
• Access to the HC communication area
• Write status and retire transfer Descriptor
6249I–ATARM–3-Oct-11
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