SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 58
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 58 of 1109
- Download datasheet (17Mb)
11.4.1
• CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 spe-
cific register behavior.
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
• L: Instruction Bit
0 = MCR instruction
1 = MRC instruction
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B.
58
31
23
15
7
AT91SAM9263
CP15 Registers Access
opcode_1
opcode_2
30
22
14
6
CP15 registers can only be accessed in privileged mode by:
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
The assembler code for these instructions is:
The MCR, MRC instructions bit pattern is shown below:
• MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register
• MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of
cond
Rd
to CP15.
CP15 to an ARM register.
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
29
21
13
5
28
20
12
L
4
1
27
19
11
1
1
3
26
18
10
1
1
2
CRm
CRn
25
17
1
1
9
1
6249I–ATARM–3-Oct-11
24
16
0
8
1
0
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