SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 1092

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1092
Revision
6249E
AT91SAM9263
Comments (Continued)
UDP:
Section 43.6.10 ”UDP Endpoint Control and Status
regarding USB clock and system clock rate.
Updated note under code with text“....a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is
required...” Ditto for RX_DATA and TXPKTRDY bit fields
Section 43.2 ”Block
updated.
Table 43-4, ”Register
UDP_ISR reset
Section 43.6.6 ”UDP Interrupt Mask
Section 43.6 ”USB Device Port (UDP) User
TXCV typo fixed to TXVC.
Table 43-1, ”USB Endpoint
Section 43.5.2.9 ”Transmit Data
Section 43.6.9 ”UDP Reset Endpoint
“TXPKTRDY: Transmit Packet Ready”
UHP:
Section 38.1
USART
Section 34.6.3.1 ”Transmitter
Section 34.6.5 ”IrDA
Figure 31-1, “USART Block
“AT91SAM9263 Electrical Characteristics”
Table 47-2, ”DC
Section 47.10.1
Figure 47-14, “USB Data Signal Rise and Fall
“AT91SAM9263 Ordering Information”
New Ordering Code: AT91SAM9263B-CU, added to
”AT91SAM9263 Errata - Revision “A” Parts”
Section 50.2.2.2 ”TDGC Clipping
Section 50.2.9.2 ”LCD Periodic Bad
Section 50.2.14 ”Static Memory Controller
”AT91SAM9263 Errata - Revision “B” Parts”
Section 50.3.2.2 ”TDGC Clipping
Section 50.3.8.2 ”LCD Periodic Bad
Section 50.3.14.6 ”SPI: SPI Software Reset Must Be Written
Section 50.3.13 ”Static Memory Controller
”Overview”, created hyperlink to “Open HCI Rev1.0 Specification”.
”SPI”: the
Characteristics”, V
Diagram”, in 2nd paragraph under the block diagram, peripheral clock requirements
Mode”, updated with instructions to receive IrDA signals.
Mapping”, UDP_CSR, UDP_FDR updated with indexed offsets. Footnote added to
Figure 47-8 on page 1051
Description”, footnote added to Dual-Bank heading
Diagram”, updated signal directions from to PIO.
Operations”, last paragraph updated.
Cancellation”, added to datasheet.
Function”, added to errata.
Function”, added to errata.
OL
Register”, bit 12 defined as BIT12, cannot be masked.
Pixels”, 16-word and 4-word offset requirements text updated.
Pixels”, 16-word and 4-word offset requirements text updated.
Register”, added steps to clear endpoints below warning.
and V
bit field description in USB_CSR, updated “Write: 0 =...”
(SMC)”,
(SMC)”,
OH
Interface”, reset value for UDP_RST_EP is 0x0000_0000
TImes”, R
lines updated.
”SMC Chip Select Parameters
”SMC Chip Select Parameters
Register”, update to code and added instructions
Table 49-1, ”AT91SAM9263 Ordering
and
EXT
Figure 47-9 on page 1051
= 27Ω.
Twice”, added to errata.
Modification”, added
Modification”, added
renamed.
Information”.
6249I–ATARM–3-Oct-11
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