SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 73

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

12.5.5.3
12.5.6
12.5.6.1
6249I–ATARM–3-Oct-11
IEEE 1149.1 JTAG Boundary Scan
Application Board Restriction
JTAG Boundary Scan Register
The TCLK signal needs to be set with care, some timing parameters are required. See “ETM
Timings” for more details.
The specified target system connector is the AMP Mictor connector.
The connector must be oriented on the application board as described below in
view of the PCB is shown from above with the trace connector mounted near the edge of the
board. This allows the Trace Port Analyzer to minimize the physical intrusiveness of the inter-
connected target.
Figure 12-6. AMP Mictor Connector Orientation
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
The Boundary Scan Register (BSR) contains 664 bits that correspond to active pins and associ-
ated control signals.
38 37
2
1
AT91SAM9263-based
Application Board
Pin 1Chamfer
AT91SAM9263
Figure
12-6. The
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