SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 272

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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AT91SAM9263
DMA transfer: Software controls the number of blocks in a DMAC transfer. Once the DMA
transfer has completed, then hardware within the DMAC disables the channel and can generate
an interrupt to signal the completion of the DMA transfer. You can then re-program the channel
for a new DMA transfer.
Single-block DMA transfer: Consists of a single block.
Multi-block DMA transfer: A DMA transfer may consist of multiple DMAC blocks. Multi-block
DMA transfers are supported through block chaining (linked list pointers), auto-reloading of
channel registers, and contiguous blocks. The source and destination can independently select
which method to use.
Scatter: Relevant to destination transfers within a block. The destination AMBA address is
incremented/decremented by a programmed amount when a scatter boundary is reached. The
number of AMBA transfers between successive scatter boundaries is under software control.
Gather: Relevant to source transfers within a block. The source AMBA address is incre-
mented/decremented by a programmed amount when a gather boundary is reached. The
number of AMBA transfers between successive gather boundaries is under software control.
Channel locking: Software can program a channel to keep the AHB master interface by locking
the arbitration for the master bus interface for the duration of a DMA transfer, block, or transac-
tion (single or burst).
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting
hlock for the duration of a DMA transfer, block, or transaction (single or burst). Channel locking
is asserted for the duration of bus locking at a minimum.
FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the
FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is
greater than or equal to half full to send data to the destination peripheral. Thus, the channel can
transfer the data using AMBA bursts, eliminating the need to arbitrate for the AHB master inter-
face for each single AMBA transfer. When this mode is not enabled, the channel only waits until
the FIFO can transmit/accept a single AMBA transfer before requesting the master bus
interface.
Pseudo fly-by operation: Typically, it takes two AMBA bus cycles to complete a transfer, one
for reading the source and one for writing to the destination. However, when the source and des-
tination peripherals of a DMA transfer are on different AMBA layers, it is possible for the DMAC
to fetch data from the source and store it in the channel FIFO at the same time as the DMAC
extracts data from the channel FIFO and writes it to the destination peripheral. This activity is
– Linked lists (block chaining) – A linked list pointer (LLP) points to the location in
– Auto-reloading – The DMAC automatically reloads the channel registers at the end
– Contiguous blocks – Where the address between successive blocks is selected to
burst transaction length is under program control and normally bears some
relationship to the FIFO sizes in the DMAC and in the source and destination
peripherals.
system memory where the next linked list item (LLI) exists. The LLI is a set of
registers that describe the next block (block descriptor) and an LLP register. The
DMAC fetches the LLI at the beginning of every block when block chaining is
enabled.
of each block to the value when the channel was first enabled.
be a continuation from the end of the previous block.
6249I–ATARM–3-Oct-11