SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 305

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.4.4
Name: DMAC_CTLxL
Addresses:0x00800018 [0], 0x00800070 [1]
Access: Read-write
Reset: 0x0
The address offset for each channel is: 0x18+[x * 0x58]
For example, CTL0: 0x018, CTL1: 0x070, etc.
This register contains fields that control the DMA transfer. The DMAC_CTLxL register is part of the block descriptor (linked
list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block
chaining is enabled.
• INT_EN: Interrupt Enable Bit
If set, then all five interrupt generating sources are enabled.
• DST_TR_WIDTH: Destination Transfer Width
• SRC_TR_WIDTH: Source Transfer Width
• DINC: Destination Address Increment
Indicates whether to increment or decrement the destination address on every destination AMBA transfer. If your device is
writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”.
00 = Increment
01 = Decrement
1x = No change
6249I–ATARM–3-Oct-11
SRC_TR_WIDTH/DST_TR_WIDTH
000
001
010
Other
DINC
DMS
31
23
15
–
7
SRC_MSIZE
Control Register for Channel x Low
30
22
14
–
6
SRC_TR_WIDTH
TT_FC
29
21
13
–
5
Size (bits)
8
16
32
Reserved
DEST_MSIZE
LLP_S_EN
28
20
12
4
LLP_D_EN
27
19
11
3
-
DST_TR_WIDTH
D_SCAT_EN
26
18
10
2
SINC
SMS
S_GATH_EN
AT91SAM9263
25
17
9
1
SRC_MSIZE
INT_EN
DINC
DMS
24
16
8
0
305