SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 182

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.6.2
21.6.2.1
21.6.2.2
182
A[0..14]
D[0..31]
(Not used A12)
AT91SAM9263
32-bit SDRAM
Hardware Configuration
Software Configuration
CFIOR_NBS1_NWR1
SDCS_NCS1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
A0
SDA10
SDCKE
SDCK
SDWE
BA0
BA1
CAS
RAS
The following configuration has to be performed:
The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed
with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO
controller.
EBI1 SDCS, SDWE, SDCKE, SDA10, RAS and CAS signals are multiplexed with PIO lines and
thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in
“SDRAM Controller (SDRAMC)”.
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
Select Assignment Register located in the bus matrix memory space.
1%6
1%6
SDA10
BA0
BA1
SDCKE
SDCK
CAS
RAS
SDWE
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
U1
U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
A12
N.C
CKE
CLK
DQML
DQMH
CAS
RAS
WE
CS
MT48LC16M16A2
MT48LC16M16A2
256 Mbits
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VSS
VSS
VSS
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
C1 100NF
C1 100NF
C2 100NF
C2 100NF
C3 100NF
C3 100NF
C4 100NF
C4 100NF
C5 100NF
C5 100NF
C6 100NF
C6 100NF
C7 100NF
C7 100NF
TSOP54 PACKAGE
CFIOW_NBS3_NWR3
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A13
A14
A1
1%6
1%6
SDA10
BA0
BA1
SDCKE
SDCK
CAS
RAS
SDWE
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
U2
U2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
A12
N.C
CKE
CLK
DQML
DQMH
CAS
RAS
WE
CS
MT48LC16M16A2
MT48LC16M16A2
256 Mbits
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VSS
VSS
VSS
6249I–ATARM–3-Oct-11
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
3V3
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C8 100NF
C8 100NF
C9 100NF
C9 100NF
C10 100NF
C10 100NF
C11 100NF
C11 100NF
C12 100NF
C12 100NF
C13 100NF
C13 100NF
C14 100NF
C14 100NF