SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 620
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 620 of 1109
- Download datasheet (17Mb)
36.6.2.1
36.6.2.2
620
AT91SAM9263
AC97 Controller Setup
Transmit Operation
The following operations must be performed in order to bring the AC97 Controller into an operat-
ing state:
The application must perform the following steps in order to send data via a channel to the AC97
Codec:
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically
set by the AC97 Controller which allows the application to start a new write action. The applica-
tion can also wait for an interrupt notice associated with TXRDY in order to send data. The
interrupt remains active until TXRDY flag is cleared.
1. Enable the AC97 Controller clock in the PMC controller.
2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register
3. Configure the input channel assignment by controlling the AC97 Controller Input
4. Configure the output channel assignment by controlling the AC97 Controller Input
5. Configure sample width for Channel A, Channel B by writing the SIZE bit field in AC97C
6. Configure data Endianness for Channel A, Channel B by writing CEM bit field in
7. Configure the PIO controller to drive the RESET signal of the external Codec. The
8. Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CxMR register.
• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status
• Write data to the AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
Register (AC97_CxSR). x being one of the
(AC97C_MR).
Assignment Register (AC97C_ICA).
Assignment Register (AC97C_OCA).
Channel x Mode Register (AC97C_CAMR), (AC97C_CBMR). The application can write
10, 16, 18,or 20-bit wide PCM samples through the AC97 interface and they will be
transferred into 20-bit wide slots.
(AC97C_CAMR), (AC97C_CBMR) register. Data on the AC-link are shifted MSB first.
The application can write little- or big-endian data to the AC97 Controller interface.
RESET signal must fulfill external AC97 Codec timing requirements.
2
channels.
6249I–ATARM–3-Oct-11
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