SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 349
SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 349 of 1109
- Download datasheet (17Mb)
28.3
28.4
6249I–ATARM–3-Oct-11
Processor Clock Controller
USB Clock Controller
Figure 28-1. Master Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock which
is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the prod-
uct. and entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by
any enabled fast or normal interrupt, or by the reset of the product.
Note:
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see
When the PLL B output is stable, i.e., the LOCKB is set:
• The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit
in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz
signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
MAINCK
PLLACK
PLLBCK
SLCK
The ARM Wait for Interrupt mode is entered with CP15 coprocessor operation. Refer to the Atmel
application note,
6217.
PMC_MCKR
CSS
Optimizing Power Consumption of AT91SAM9261-based
PMC_MCKR
Master Clock
Prescaler
PRES
PMC_MCKR
Master
Divider
MDIV
Clock
Figure
AT91SAM9263
28-2).
MCK
To the Processor
Clock Controller (PCK)
Systems, lit. number
349
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