ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 42

• Manufacturer Part Number: ATmega32
• Manufacturer: Atmel Corporation

Specifications of ATmega32

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Watchdog Timer
Control Register –
WDTCR
2503Q–AVR–02/11
• Bits [7:5] – Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
• Bits [2:0] – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 17. Watchdog Timer Prescale Select
Bit
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
ten to WDE even though it is set to one before the disable operation starts.
WDP1
0
0
1
1
0
0
1
1
Table
R
7
–
0
WDP0
17.
0
1
0
1
0
1
0
1
R
6
–
0
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
Typical Time-out
at V
WDP2
17.1ms
34.3ms
68.5ms
R/W
CC
0.14s
0.27s
0.55s
2
0
1.1s
2.2s
= 3.0V
WDP1
R/W
1
0
Typical Time-out
ATmega32(L)
WDP0
at V
R/W
0
0
16.3ms
32.5ms
0.13 s
65ms
0.26s
0.52s
CC
1.0s
2.1s
= 5.0V
WDTCR
42