ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 24

• Manufacturer Part Number: ATmega32
• Manufacturer: Atmel Corporation

Specifications of ATmega32

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

System Clock
and Clock
Options
Clock Systems
and their
Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
Asynchronous Timer
Clock – clk
2503Q–AVR–02/11
ASY
I/O
CPU
FLASH
Figure 11
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 11. Clock Distribution
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Coun-
ter as a real-time counter even when the device is in sleep mode.
Timer/Counter
Timer/Counter
Asynchronous
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
I/O
is halted, enabling TWI address reception in all sleep modes.
General I/O
Modules
External RC
Oscillator
clk
clk
ASY
I/O
32. The clock systems are detailed
External Clock
ADC
Control Unit
AVR Clock
Multiplexer
clk
Clock
ADC
Source Clock
CPU Core
clk
Oscillator
clk
Crystal
CPU
Reset Logic
FLASH
Watchdog Clock
Crystal Oscillator
RAM
Low-frequency
Watchdog Timer
Figure
ATmega32(L)
Watchdog
Oscillator
11.
Flash and
EEPROM
“Power Manage-
Calibrated RC
Oscillator
24