ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 119

• Manufacturer Part Number: ATmega32
• Manufacturer: Atmel Corporation

Specifications of ATmega32

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Normal Mode
Clear Timer on
Compare Match (CTC)
Mode
2503Q–AVR–02/11
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (
timer clock cycle as the TCNT2 becomes zero. The
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the
are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in normal mode is not recommended, since this will occupy
too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manip-
ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also sim-
plifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT2 and OCR2, and then counter (TCNT2)
is cleared.
Figure 57. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the
TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2 is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the
TCNTn
OCn
(Toggle)
Period
1
TOV2
Flag, the timer resolution can be increased by software. There
2
3
TOV2
Figure
4
Flag in this case behaves like a ninth
57. The counter value (TCNT2)
TOV2
ATmega32(L)
OCn Interrupt Flag Set
) will be set in the same
(COMn1:0 = 1)
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