AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 6

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

6
P6.0-P6.1
Reset
ALE/PROG
PSEN
EA
XTAL1
XTAL2
Tx_OCD
Rx_OCD
Mnemonic
AT89C51RE2
12,34
LCC
15
16
17
18
19
12
12
34
34
10
33
32
35
21
20
23
1
Pin Number
VQFP 1.4
6, 28
10
12
13
28
28
27
26
29
15
14
17
39
11
9
6
6
4
Type
O (I)
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
Name and Function
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Port 6: Port 6 is an 2-bit bidirectional I/O port with internal pull-ups. Port 6 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 6 pins that are externally pulled low will source current because of the internal pull-ups.
Port 6 also serves some special features as listed below.
RXD_1 (P6.0): Serial input port
SDA (P6.0) : TWI Serial Data
SDA is the bidirectional TWI data line.
TXD_1 (P6.1) : Serial output port
SCL ( P6.1) : TWI Serial Clock
SCL output the serial clock to slave peripherals.
SCL input the serial clock from master.
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
capacitor to V
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG) during Flash programming. ALE
can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during
internal fetches.
Program Store ENable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
External Access Enable: EA must be externally held low to enable the device to fetch code
from external program memory locations 0000H to FFFFH (RD). If security level 1 is
programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier
Tx_OCD: On chip debug Serial output port
Rx_OCD: On chip debug Serial input port
CC
. This pin is an output when the hardware watchdog forces a system reset.
SS
permits a power-on reset using only an external
7663E–8051–10/08