AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 125

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AT89C51RE2

Manufacturer Part Number
AT89C51RE2
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C51RE2

Flash (kbytes)
128 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
34
Spi
1
Uart
2
Sram (kbytes)
8.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/OCD
Watchdog
Yes

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WDT During Power
Down and Idle
7663E–8051–10/08
Table 93. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value = XXXX X000
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power
Down mode the user does not need to service the WDT. There are 2 methods of exiting Power
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power Down mode. When Power Down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C51RE2 is reset. Exiting Power
Down with an interrupt is significantly different. The interrupt is held low long enough for the
oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-
ter to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RE2 while in Idle mode, the user should always set up a timer that will periodically exit
Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic
Bit
S2
S1
S0
6
-
-
-
-
-
-
Description
Reserved
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2
0
0
0
0
1
1
1
1
5
-
The value read from this bit is undetermined. Do not try to set this bit.
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
4
-
Selected Time-out
(2
(2
(2
(2
(2
(2
(2
(2
14
15
16
17
18
19
20
21
- 1) machine cycles, 16. 3 ms @ F
- 1) machine cycles, 32.7 ms @ F
- 1) machine cycles, 65. 5 ms @ F
- 1) machine cycles, 131 ms @ F
- 1) machine cycles, 262 ms @ F
- 1) machine cycles, 542 ms @ F
- 1) machine cycles, 1.05 s @ F
- 1) machine cycles, 2.09 s @ F
3
-
S2
2
AT89C51RE2
OSCA
OSCA
S1
OSCA
OSCA
OSCA
1
OSCA
OSCA
OSCA
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
=12 MHz
S0
0
125

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