AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 36

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Access and
Operations
Descriptions
FM0 FLASH Registers
BMSEL Register
36
AT89C51RE2
The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA
register.
These registers are used to map the columns latch, HSB, FCB and extra row in the working data
or code space.
Table 22. BMSEL Register
BMSEL Register (S:92h)
Bank Memory Select
Reset Value= 0000 0YYYb (where YYY depends on BRV2:0 value in Fuse Configuration Byte)
Bit Number
MBO2
7-5
4-3
2-0
7
Mnemonic
MBO2:0
MBO1
FBS2:0
Bit
6
Description
Memory Bank Operation
These bits select the target memory bank for flash write or read operation. These bits
allows to read or write the on-chip flash memory from one upper 32K bytes to another
one.
0 X X: The on-chip flash operation target banked is the same as FBS2:0
1 0 0: The target memory bank is forced to Bank0
1 0 1: The target memory bank is forced to Bank1
1 1 0: The target memory bank is forced to Bank2
1 1 1: The target memory bank is forced to Bank3 (optional External bank)
Reserved
Fetch Bank Selection
These bits select the upper 32K bytes execution bank:
FBS1:0 can be read/write by software.
FBS2 is read-only by software (the Boot bank can not be mapped from FM0)
0 0 0 Bank0
0 0 1 Bank1
0 1 0 Bank2
0 1 1 Bank3 (optionnal external bank)
1 X X Boot Bank (Read only)
Upon reset FBS2:0 is initialized according to BRV2:0 configuration bits in FCB.
MBO0
5
4
3
FBS2
2
FBS1
1
7663E–8051–10/08
FBS0
0