AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 150

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Baud Rate
150
AT89C51RE2
In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI
Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error
conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
Note:
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by
three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one
of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128.
Table 113 gives the different clock rates selected by SPR2:SPR1:SPR0.
In Slave mode, the maximum baud rate allowed on the SCK input is limited to F
Table 113. SPI Master Baud Rate Selection
SPR2
The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind
of configuration can be found when only one Master is driving the network and there is no
way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSCR will never
be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
configuration can happen when the system includes one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master
uses the SS pin to select the communicating Slave device.
0
0
0
0
1
1
1
1
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this
(1)
mode, the SS is used to start the transmission.
.
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
F
F
F
F
F
CLK PERIPH
F
Clock Rate
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
Don’t Use
CLK PERIPH
Don’t Use
/128
/16
/32
/64
/8
/4
Baud Rate Divisor (BD)
No BRG
No BRG
(2)
128
sys
16
32
64
4
8
. This kind of
7663E–8051–10/08
/4