AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 35

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Column latches
Cross Memory Access
Description overview
7663E–8051–10/08
The column latches, also part of FM0, has a size of one page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations (user array,
XROW, Hardware security byte and Fuse Configuration Byte).
This block is write only from FM0, RM0.
The FM0 memory can be programmed from RM0 without entering idle mode.
Programming FM0 from FM0 makes the CPU core entering “pseudo idle” mode.
In the pseudo idle mode, the code execution is halted, the peripherals are still running (like stan-
dard idle mode) but all interrupt are delayed to the end of this mode. There are fours ways of
exiting pseudo idle mode:
•
•
•
•
Programming FM0 from external memory code (EA=0 or EA=1,with Bank3 active) is impossible.
If a reset occurs during flash programming the target page could be incompletely erased or pro-
grammed, but any other memory location (FM0, RAM, XRAM) remain unchanged.
The Table 21 shows all software flash access allowed.
Table 21. Cross Memory Access
1.
N.A. Not applicable
At the end of the regular flash programming operation
Reset the chip by external reset
Reset the chip by hardware watchdog
Reset the chip by PCA watchdog
External memory
Depends of general lock bits configuration
EA=1, Bank3
(user Flash)
(boot ROM)
EA = 0
RM0
FM0
or
Load column latch
Load column latch
Load column latch
Action
Read
Read
Read
Write
Write
Write
ok (pseudo idle mode)
(user Flash)
Denied
Denied
FM0
ok
ok
ok
ok
ok
(1)
AT89C51RE2
(boot ROM)
Denied
Denied
RM0
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
ok
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