AT89C51RE2 Atmel Corporation, AT89C51RE2 Datasheet - Page 47

• Manufacturer Part Number: AT89C51RE2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RE2

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Spi: 1
• Uart: 2
• Sram (kbytes): 8.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/OCD
• Watchdog: Yes

Errors Report /
Miscellaneous states
Flash Busy flag
Flash Programming
Sequence Error
Power Down Mode
Request
7663E–8051–10/08
The FBUSY flag indicates on-going flash write operation.
The busy flag is set by hardware, the hardware clears this flag after the end of the programming
operation.
When a wrong sequence is detected the FSE in FSTA is set.
The following events are considered as not correct activation sequence:
- The two “MOV FCON,5x and MOV FCON, Ax” were not consecutive, or the second instruction
differs from “MOV FCON Ax” (for example, an interrupt occurs during the sequence).
- The sequence (write flash or reset column latches) occurred with no data loaded in the column
latches
The FSE bit can be cleared:
- By software
- By hardware when a correct programming sequence occurs.
Note: When a good sequence occurs just after an incorrect sequence, the previous error is lost.
The user software application should take care to check the FSE bit before initiating a new
sequence.
In Power Down mode, the on-chip flash memory is deselected (to reduce power consumption),
this leads to the lost of the columns latches content.
In this case, if columns latches were previously loaded they are reset: FLOAD bit in FSTA regis-
ter should be reset after power down mode.
If a power down mode is requested during flash programming (FBUSY=1), all power down
sequence instructions should be ignored until the end of flash process.
AT89C51RE2
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