GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 98

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
10.3.3
10.3.4
10.3.5
10.3.6
90
Register 18: PHY Address Register
Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
2
1
0
15:5
4:0
15:0
15:0
15:0
Bit(s)
Bit(s)
Bit(s)
Bit(s)
Bit(s)
Extended
Squelch
Link Integrity
Disable
Jabber Function
Disable
Reserved
PHY Address
Receive False
Carrier
Disconnect Event
Receive Error
Frame
Name
Name
Name
Name
Name
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
1 = Link disabled
0 = Normal Link Integrity operation
1 = Jabber disabled
0 = Normal Jabber operation
These bits are reserved and should be set to a
constant ‘0’
These bits are set to the PHY’s address, 00001b.
These bits are used for the false carrier counter.
This field contains a 16-bit counter that increments for
each disconnect event. The counter freezes when full
and self-clears on read
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter freezes when full and self-clears
on read.
Description
Description
Description
Description
Description
Default
Default
Default
Default
Default
--
--
--
0
0
0
0
1
Datasheet
RW
RW
RW
RO
RO
RO
SC
RO
SC
RO
SC
R/W
R/W
R/W
R/W
R/W