GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 102

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
11.3.2
94
NAND Tree
The NAND Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82559 to be validated at board test. The NAND Tree was chosen for its speed
advantages. Modern automated test equipment can perform a complete peripheral scan without
support at the board level. This command connects all outputs of the input buffers in the device
periphery into a NAND Tree scheme. All the output drivers of the output buffers, except the Test
Port Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of
the tree. There are two separate chains and associated outputs for speed. Any hard strapped pins
will prevent the tester from scanning correctly. This mode is entered by placing the test pins in the
following combination:
There are two NAND Tree chains with two separate outputs assigned to FLOE# (Chain 1) and
FLWE# (Chain 2).
TEST = 1
TCK = 0
Table 26. NAND Tree Chains
(NAND Tree Output)
Chain Order
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
TEXEC = 1
TI = 1
DEVSEL#
FRAME#
(FLOE#)
Chain 1
C/BE2#
C/BE1#
SERR#
TRDY#
STOP#
PERR#
IDSEL
IRDY#
REQ#
INTA#
RST#
GNT#
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CLK
PAR
SPEEDLED
SMBALRT#
CSTSCHG
ISOLATE#
CLKRUN#
ACTLED#
ALTRST#
(FLWE#)
SMBCLK
Chain 2
C/BE3#
SMBD
LILED
PME#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
FLD0
FLD1
FLD2
FLD3
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