GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 68

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
8.1.9.1
8.1.9.2
8.1.9.3
8.1.9.4
60
Figure 26. Base Address Register for I/O Mapping
Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory
or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that
map to I/O space must return 1b in bit 0.
Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is
reserved and must return 0b on reads, and the other bits are used to map the device into I/O space.
The number of upper bits that a device actually implements depends on how much of the address
space the device will respond to. For example, a device that wants a 1 Mbyte memory address
space would set the most significant 12 bits of the base address register to be configurable, setting
the other bits to 0b.
The 82559 contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.
CSR Memory Mapped Base Address Register
The 82559 requires one BAR for memory mapping. Software determines which BAR, memory or
I/O, is used to access the 82559 CSR registers.
The memory space for the 82559 CSR Memory Mapped BAR is 4 Kbytes. The space is marked as
not prefetchable and is mapped anywhere in the 32-bit memory address space.
CSR I/O Mapped Base Address Register
The 82559 requires one BAR for I/O mapping. Software determines which BAR, memory or I/O, is
used to access the 82559 CSR registers. The I/O space for the 82559 CSR I/O BAR is 64 bytes.
Flash Memory Mapped Base Address Register
The Flash Memory BAR is a Dword register. The 82559 physically supports a 128 Kbyte Flash
device. In a CardBus system, the upper section of the memory mapped window (above the physical
Flash device) is used for CIS information. The 82559 claims a window of 128 Kbytes in CardBus
mode and always claims a Flash memory window, regardless of whether or not a Flash device is
connected.
Expansion ROM Base Address Register
The Expansion ROM has a memory space of 1 Mbyte and its BAR is a Dword register that supports
a 128 Kbyte memory via the 82559 local bus. The Expansion ROM BAR can be disabled by setting
the Boot Disable bit of the EEPROM (word AH, bit 11). If the Boot Disable bit is set, the 82559
returns a 0b for all bits in this address register, avoiding request of memory allocation for this
space. In LAN/modem combination designs using Flash, this bit controls the state of the CFCS#
signal (pin L7) and is cleared after the initial access of the expansion ROM area. Therefore, in a
31
Reserved
I/O space indicator
Base Address
2 1
0
1
0
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