GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 49

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

5.1.2.3
5.1.2.4
Datasheet
Figure 13. NRZ to MLT-3 Encoding Diagram
Figure 14. Conceptual Transmit Differential Waveform
When an NRZ “0” arrives at the input of the encoder, the last output level is maintained (either
positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to
the next level. The order of steps is negative-zero-positive-zero which continues periodically.
100BASE-TX Transmit Framing
The PHY unit does not differentiate between the fields of the MAC frame containing preamble,
Start of Frame Delimiter, data and Cyclic Redundancy Check (CRC). The PHY unit encodes the
first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/
5B lookup table, and adds the “TR” code after the end of the packet. The PHY unit scrambles and
serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives it onto the wire.
Transmit Driver
The transmit differential pair lines are implemented with a digital slope controlled current driver
that meets the TP-PMD specifications. Current is sinked from the isolation transformer by the TDP
and TDN pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the
following figure.
(V
+1V
-1V
Clock
NRZ
NRZ1
MLT-3
0V
TDP
I
-V
TDN
)
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
Networking Silicon — 82559
0
0
0
0
0
0
1
1
1
t
41