GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 6

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
6.0
7.0
8.0
vi
5.2
5.3
5.4
82559 Modem Functionality ............................................................................................. 49
6.1
6.2
6.3
82559 TCO Functionality ................................................................................................. 51
7.1
7.2
7.3
PCI and CardBus Configuration Registers....................................................................... 55
8.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
10BASE-T Functionality ...................................................................................... 44
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
Auto-Negotiation Functionality ............................................................................ 46
5.3.1
5.3.2
LED Description .................................................................................................. 47
PCI Address Mapping to the Modem .................................................................. 49
Modem Read and Write Cycles .......................................................................... 49
Modem and Preboot eXtension Environment Coexistence................................. 49
6.3.1
6.3.2
System Functionality with a TCO Controller ....................................................... 51
System Functionality without a TCO Controller .................................................. 53
TCO Interface...................................................................................................... 53
7.3.1
7.3.2
Function 0: LAN (Ethernet) PCI Configuration Space......................................... 55
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10 Base Address Registry Summary .......................................................... 61
8.1.11 CardBus Card Information Structure (CIS) Pointer ................................ 61
8.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers....................... 61
8.1.13 Capability Pointer ................................................................................... 62
8.1.14 Interrupt Line Register............................................................................ 62
8.1.15 Interrupt Pin Register ............................................................................. 62
8.1.16 Minimum Grant Register ........................................................................ 62
100BASE-TX Transmit Clock Generation .............................................. 39
100BASE-TX Transmit Blocks ............................................................... 39
100BASE-TX Receive Blocks ................................................................ 42
100BASE-TX Collision Detection ........................................................... 43
100BASE-TX Link Integrity and Auto-Negotiation Solution.................... 43
Auto 10/100 Mbps Speed Selection....................................................... 43
10BASE-T Transmit Clock Generation................................................... 44
10BASE-T Transmit Blocks.................................................................... 44
10BASE-T Receive Blocks..................................................................... 44
10BASE-T Collision Detection................................................................ 45
10BASE-T Link Integrity ......................................................................... 45
10BASE-T Jabber Control Function....................................................... 45
10BASE-T Full Duplex ........................................................................... 46
Description ............................................................................................. 46
Parallel Detect and Auto-Negotiation ..................................................... 46
Programming Details.............................................................................. 49
Support Circuitry .................................................................................... 50
SMB Alert Signal (SMBALRT#).............................................................. 53
Alert Response Address (ARA) Cycle.................................................... 54
PCI Vendor ID and Device ID Registers ................................................ 55
PCI Command Register ......................................................................... 56
PCI Status Register................................................................................ 57
PCI Revision ID Register........................................................................ 58
PCI Class Code Register ....................................................................... 58
PCI Cache Line Size Register................................................................ 58
PCI Latency Timer ................................................................................. 59
PCI Header Type ................................................................................... 59
PCI Base Address Registers.................................................................. 59
Datasheet