GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 63

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

8.0
8.1
8.1.1
Datasheet
Figure 21. PCI Configuration Registers
PCI and CardBus Configuration Registers
The 82559 acts as both a master and a slave on the PCI bus. As a master, the 82559 interacts with
the system main memory to access data for transmission or deposit received data. As a slave, some
82559 control structures are accessed by the host CPU to read or write information to the on-chip
registers. The CPU also provides the 82559 with the necessary commands and pointers that allow it
to process receive and transmit data.
Function 0: LAN (Ethernet) PCI Configuration Space
The 82559 PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82559 are both read only word entities. Their values are:
Vendor ID: 8086H
Device ID: 1229H
Reserved
Max_Lat
Power Management Capabilities
BIST
Figure
Subsystem ID
21.
Device ID
Status
Flash Memory Mapped Base Address Register
CSR Memory Mapped Base Address Register
Header Type
CSR I/O Mapped Base Address Register
Expansion ROM Base Address Register
Reserved (PCI)/CIS Pointer (CardBus)
Class Code
Min_Gnt
Reserved
Reserved Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Data
Reserved
Latency Timer
Next Item Ptr
Interrupt Pin
Power Management CSR
Subsystem Vendor ID
Command
Vendor ID
Networking Silicon — 82559
Cache Line Size
Interrupt Line
Capability ID
Revision ID
Cap_Ptr
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
DCH
E0H
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