GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 34

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
4.2.4
4.3
4.3.1
4.3.1.1
26
Power Management Event and Card Status Change Signals
The 82559 supports power management indications in both the PCI and CardBus mode. In
CardBus systems, the CSTSCHG pin is used for power management event indication. The PME#
output pin provides an indication of a power management event in PCI systems. The CSTSCHG
pin is supported by four registers located in the Control/Status Register
Status Registers” on page 71
PCI Power Management
In addition to the base functionality of the 82558 B-step, the 82559 supports a larger set of wake-up
packets and the capability to wake the system on a link status change from a low power state. These
added power management enhancements enable the 82559 to adhere to emerging standards. The
82559 enables the host system to be in a sleep state and remain virtually connected to the network.
After a power management event or link status change is detected, the 82559 will wake the host
system. The sections below describe these events, the 82559 power states, and estimated power
consumption at each power state.
Power States
The 82559 contains two sets of power management registers, one for PCI and one for CardBus, and
implements all four power states as defined in the Power Management Network Device Class
Reference Specification, Revision 1.0. The four states, D0 through D3, vary from maximum power
consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in
the D0 state, except for host accesses to the 82559’s PCI configuration registers. The D1 and D2
power management states enable intermediate power savings while providing the system wake-up
capabilities. In the D3
is supplied. Wake-up indications from the 82559 are provided by the Power Management Event
(PME#) signal in PCI implementations and the Card Status Change (CSTSCHG) signal in CardBus
designs.
In addition to providing a host interface through the PCI bus, the 82559 provides TCO controller
access through a dedicated System Management Bus (SMB). Additional information on the
supported TCO functionality at all power states is described in
Functionality” on page
D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82559 receives full power and should be providing full
functionality. In the 82559 the D0 state is partitioned into two substates, D0 Uninitialized (D0u)
and D0 Active (D0a).
•
•
•
•
Event Register
Mask Register
Present State Register
Force Event Register
cold
51.
state, the 82559 can provide wake-up capabilities only if auxiliary power
describes these registers in more detail):
Section 7.0, “82559 TCO
(Section 9.0, “Control/
Datasheet