GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 94

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
10.1.2
86
Register 1: Status Register Bit Definitions
9
8
7
6:0
15
14
13
12
11
10:7
6
5
4
3
2
1
0
Bit(s)
Bit(s)
Reserved
100BASE-TX Full
Duplex
100 Mbps Half
Duplex
10 Mbps Full
Duplex
10 Mbps Half
Duplex
Reserved
Management
Frames Preamble
Suppression
Auto-Negotiation
Complete
Remote Fault
Auto-Negotiation
Ability
Link Status
Jabber Detect
Extended
Capability
Restart Auto-
Negotiation
Duplex Mode
Collision Test
Reserved
Name
Name
This bit is reserved and should be set to 0b.
1 = PHY able to perform full duplex 100BASE-TX
1 = PHY able to perform half duplex 100BASE-TX
1 = PHY able to operate at 10Mbps in full duplex
mode
1 = PHY able to operate at 10 Mbps in half duplex
mode
These bits are reserved and should be set to 0000b.
0 = PHY will not accept management frames with
preamble suppressed
1 = Auto-Negotiation process completed
0 = Auto-Negotiation process has not completed
0 = No remote fault condition detected
1 = PHY is able to perform Auto-Negotiation
1 = Valid link has been established
0 = Invalid link detected
1 = Jabber condition detected
0 = No jabber condition detected
1 = Extended register capabilities enabled
This bit restarts the Auto-Negotiation process and is self-
clearing.
1 = Restart Auto-Negotiation process
is disabled. If the PHY reports that it is only able to
operate in one duplex mode, the value of this bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit,
bit 8.
1 = Full Duplex
0 = Half Duplex
This bit will force a collision in response to the assertion
of the transmit enable signal.
1 = Force COL
0 = Do not force COL
This bit controls the duplex mode when Auto-Negotiation
These bits are reserved and should be set to 0000000b.
Description
Description
Default
0
1
1
1
1
0
0
0
0
1
0
0
1
Default
0
0
0
0
Datasheet
RO
E
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
LL
RO
LH
RO
R/W
R/W
RW
SC
RW
RW
RW