GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 28

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
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Figure 5. Flash Buffer Write Cycle
Flash buffer. When TRDY# is asserted, the 82559 drives valid data on the AD[31:0] lines. The
CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses
can be byte or word length.
Write Accesses: The CPU, as the initiator, drives the address lines
byte enable lines
with valid data immediately after asserting
asserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting
TRDY#
accesses can be byte length only.
4.2.1.1.3 Retry Premature Accesses
The 82559 responds with a Retry to any configuration cycle accessing the 82559 before the
completion of the automatic read of the EEPROM. The 82559 may continue to Retry any
configuration accesses until the EEPROM read is complete. The 82559 does not enforce the rule
that the retried master must attempt to access the same address again in order to complete any
delayed transaction. Any master access to the 82559 after the completion of the EEPROM read will
be honored.
, the 82559 signals the CPU that the current data access has completed. Flash buffer write
Figure 6
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
C/BE#[3:0] and
below depicts how a Retry looks when it occurs.
MEM WR
the control lines
ADDR
IRDY#
IRDY#
. The 82559 controls the
DATA
BE#
and
FRAME#
AD[31:0],
. It also provides the 82559
TRDY#
the command and
signal and de-
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