GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 48

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
5.1.2.2
40
100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long
transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B
encoder block and presents the scrambled data to the MLT-3 encoder. The PHY unit implements
the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation.
The cipher equation used is:
The encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the Scrambler
and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZI coding,
but three levels are output instead of two. There are three output levels: positive, negative and zero.
Table 2. 4B/5B Encoder
Symbol
D
R
H
E
F
K
T
V
V
V
V
V
V
V
V
V
V
J
I
5B Symbol Code
X[n] = X[n-11] + X[n-9] (mod 2)
10001
00000
00001
00010
00100
00101
01000
10000
11011
11100
11101
11000
01101
00111
00011
00110
01100
11001
11111
Inter Packet Idle Symbol
(No 4B)
1st Start of Packet Symbol
0101
2nd Start of Packet Symbol
0101
1st End of Packet Symbol
2nd End of Packet Symbol
and Flow Control
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
PHY based Flow Control
INVALID
4B Nibble Code
1101
1110
1111
Datasheet