GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 93

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

10.0
10.1
10.1.1
Datasheet
PHY Unit Registers
The 82559 provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms mentioned in the registers are defined as follows:
MDI Registers 0 - 7
Register 0: Control Register Bit Definitions
15
14
13
12
11
10
Bit(s)
SC:
RO:
E:
LL:
LH:
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Reserved
Self cleared.
Read only.
EEPROM setting affects content.
Latch low.
Latch high.
Name
This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
1 = PHY Reset
This bit enables loopback of transmit data nibbles from
the TXD[3:0] signals to the receive data path. The PHY
unit’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
1 = Loopback enabled
0 = Loopback disabled (Normal operation)
This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disabled.
1 = 100 Mbps
0 = 10 Mbps
This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
This bit sets the PHY unit into a low power mode. In low
power mode, the PHY unit consumes no more than 30
mA.
1 = Power-Down enabled
0 = Power-Down disabled (Normal operation)
This bit is reserved and should be set to 0b.
Description
Networking Silicon — 82559
Default
0
0
1
1
0
0
RW
SC
RW
RW
RW
RW
RW
R/W
85